H ΑΜD συνεχίζει την προέλαση (ΙΙ) προϊδεάζοντας για αύξηση επιδόσεων στις GPUs RDNA3, αντίστοιχη με αυτή που έφεραν οι RDNA2

δωσε πονο..............

lets go

Αυτό που εντυπωσιάζει είναι ότι οι άνθρωποι δεν έχουν κυκλοφορήσει ακόμα τις RDNA2 και ήδη βρίσκονται σε φάση execution με τις RDNA3 και μάλιστα δεσμεύονται για αντιστοιχη βελτίωση στις επιδόσεις. Αυτό σημαίνει ότι το προϊόν είναι ήδη τεσταρισμένο στα εργαστήριά τους. Δεν είναι τυχαία τα επιτεύγματα της ΑΜD την τελευταία 3ετία

2 hours ago, gdp77 said:

Αυτό που εντυπωσιάζει

δεν γνωρίζω αν ακολουθούν την ίδια τακτική στις κάρτες όπως στα cpu. Στα cpu έχουν δύο ανεξάρτητες μεταξύ τους ομάδες σχεδίασης. Την ίδια στιγμή που η μία ομάδα σχεδιάζει τους ΖΕΝ2 η άλλη δουλεύει ανεξάρτητα «για το επόμενο».

Αυτά είναι μεγάλα μυστικά που μου χει μάθει ο Πέτα και ένα άρθρο του Anandtech, το οποίο ίσως κάπου το έχετε βάλει ήδη αλλά το καλό αντέχει στην επανάληψη, οπότε στο ξαναβάζω ειδικά για σένα, νομίζω θα σου αρέσει.

 

By keeping the new 8-core Zen 3 chiplet the same size and same power, this obviously means that AMD had to build a core that fits within those constraints but also affords a performance and performance efficiency uplift in order to make a more compelling design. Typically when designing a CPU core, the easiest thing to do is to take the previous design and upgrade certain parts of it – or what engineers call tackling ‘the low hanging fruit’ which enables the most speed-up for the least effort. Because CPU core designs are built to a deadline, there are always ideas that never make it into the final design, but those become the easiest targets for the next generation. This is what we saw with Zen 1/Zen+ moving on to Zen 2. So naturally, the easiest thing for AMD to do would be the same again, but with Zen 3.
 

However, AMD did not do this. In our interviews with AMD’s senior staff, we have known that AMD has two independent CPU core design teams that aim to leapfrog each other as they build newer, high performance cores. Zen 1 and Zen 2 were products from the first core design team, and now Zen 3 is the product from the second design team. Naturally we then expect Zen 4 to be the next generation of Zen 3, with ‘the low hanging fruit’ taken care of.
 

In our recent interview with AMD’s Chief Technology Officer, Mark Papermaster, we were told that if you were to look at the core from a 100,000 foot level, you might easily mistake that the Zen 3 core design to be similar to that of Zen 2. However, we were told that because this is a new team, every segment of the core has been redesigned, or at the very least, updated. Users who follow this space closely will remember that the branch predictor used in Zen 2 wasn’t meant to come until Zen 3, showing that even the core designs have an element of portability to them. The fact that both Zen 2 and Zen 3 are built on the same TSMC N7 process node (the same PDK, although Zen 3 has the latest yield/consistency manufacturing updates from TMSC) also helps in that design portability.
 

AMD has already announced the major change that will be obvious to most of the techies that are interested in this space: the base core chiplet, rather than having two four-core complexes, has a single eight-core complex. This enables each core to access the whole 32 MB of L3 cache of a die, rather than 16 MB, which reduces latency of memory accesses in that 16-to-32 MB window. It also simplifies core-to-core communication within a chiplet. There are a couple of trade-offs to do this, but overall it is a good win.

In fact there are a significant number of differences throughout the core. AMD has improved:

branch prediction bandwidth
faster switching from the decode pipes to the micro-op cache,
faster recoveries from mispredicts,
enhanced decode skip detection for some NOPs/zeroing idioms
larger buffers and execution windows up and down the core,
dedicated branch pipes,
better balancing of logic and address generation,
wider INT/FP dispatch,
higher load bandwidth,
higher store bandwidth,
better flexibility in load/store ops
faster FMACs
A wide variety of faster operations (including x87?)
more TLB table walkers
better prediction of store-to-load forward dependencies
faster copy of short strings
more AVX2 support (VAES, VPCLMULQD)
substantially faster DIV/IDIV support
hardware acceleration of PDEP/PEXT
Many of these will be explained and expanded upon over the next few pages, and observed in the benchmark results. Simply put, this is something more than just a core update – these are genuinely new cores and new designs that required new sheets of paper to be built upon.